The present invention relates to an apparatus and method for addressing a cache in a computer system and, more particularly, to a cache tag memory having an integrated adder and pre-decode circuit.
A cache is a small, fast memory which stores the data that has been most recently accessed by a central processing unit (CPU). When the CPU requires a particular word or block of data, the CPU first looks in the cache. If the data is not present in the cache, the CPU retrieves the data from a remote device, such as main memory, and stores the data in the cache. If the data is present in the cache, the CPU retrieves the data from the cache, as opposed to main memory. A cache therefore limits the number of times the CPU must go to main memory to access data, which significantly increases the rate of data retrieval.
A typical cache is divided into a data memory and a tag memory. The data memory stores the data that was retrieved from main memory. The tag memory stores a portion of the address of the data that was stored in the data memory. When the CPU searches the cache, the CPU retrieves an address index corresponding to the desired data from an index register and adds an address offset to obtain a cache target address. The cache target address has a block size field, a tag size field and a tag compare field. The block size field determines the number of corresponding data blocks in the data memory that are valid if a cache hit occurs for the cache target address. The tag size field is decoded and used to drive the tag memory address bits. The tag compare field is compared with the address that is stored in the tag memory. If there is a match, the data in the data memory, and the number subsequent blocks of data determined by the block size field are valid data and can be accessed by the CPU.
When the tag size field is decoded, individual bits within the tag size field are typically paired and pre-decoded into separate nets whose active states (normally high) represent successive integer values such as 0, 1, 2, 3, etc. These nets are then further decoded by a row decode circuit and provided to word line drivers which drive the memory address lines and allow for reading from or writing to the tag memory cells. The total propagation time required to access the selected tag memory cells is the time that is required to add the address offset to the address index, plus the time that is required to pre-decode the resulting sum, plus the time that is required to perform the final row decode. This propagation time is a significant limitation in the overall speed of the cache.